1. Field of the Invention
The present invention relates to a counter, and more particularly, to a hold/reset mode selection counter.
2. Background of the Related Art
FIG. 1 is a schematic block diagram of a related art counter. As shown in FIG. 1, a plurality of counter blocks CNT1-CNT5 each has a count input terminal CI receiving a count enable signal CNTEN, a clock input terminal CP receiving an external clock signal CLK and respectively output a decode output value Q0-Q4. The plurality of counter blocks CNT1-CNT5 are connected in series. Each count input terminal CI of the counter blocks CNT1-CNT5 receives a count output signal CO from the previous counter block. In addition, a reset input terminal CDN of each of the counter blocks CNT1-CNT5 is reset by receiving a reset signal RS.
FIG. 2 is a circuit diagram of an ith counter block CNT(i) of the counter blocks CNT1-CNT5 in FIG. 1. The ith counter block CNT(i) is composed of an inverter INV1 inverting a count output signal CO(i-1) from a previous counter block CNT(i-1) a double input multiplexor MUX and a JK flipflop JKF. The JK flipflop JKF has a first input terminal J receiving the count output signal CO(i-1) from the previous counter block CNT(i-1), a second input terminal K receiving an output signal from the inverter INV1, a clock input terminal CP receiving an external clock signal CLK, the reset input terminal CDN receiving the reset signal RS and outputting an output value Q(i). The double input multiplexor MUX is enabled by the count output signal CO(i-1) from the previous counter block CNT(i-1). The double input multiplexor MUX has a first input terminal CI0 connected with ground VSS, a second input terminal CI1 receiving the output value Q(1) from the JK flipflop JFK and outputs a count output signal CO(i).
The operation of the related art counter of FIG. 1 will now be described. First, when the two input terminals J, K of the JK flipflop JKF of the counter block CNT(i) receive different inputs, the JK flipflop JKF holds or transits a previous value at each rising edge of the external clock signal CLK. Thus, when the first and second input terminals J, K of the JF flipflop JKF receive a high-level signal and a low-level signal, respectively, the output value Q is transited. However, when the first and second input terminals J, K of the JF flipflop JKF receive a low-level signal and a high-level signal, respectively, the JF flipflop JKF holds the previous value.
The multiplexor MUX of the counter block CNT(i) generates the count output signal CO(i), which is supplied to the count input terminal CI of a next counter block CNT(i+1). Only when the count output signal CO(i-1) of the previous counter block CNT(i-1) of the counter block CNT(i) is a high level, the output value Q(i) from the counter block CNT(i) is identical to the count output signal CO(i). Thus, when output values from the counter blocks CNT1-CNT5 are [00010], subsequent output values are prevented from becoming [00111], and instead become [00011].
Accordingly, when the count enable signal CNTEN is a high level, the related art counter in FIG. 1 counts from [00000] to [11111] and is reset by the reset signal RS. The related counter counts up to and holds a predetermined count value and waits for a new control signal holding the value. However, as described above, the related art counter has various disadvantages. The related art counter may have a redundant desirable counter value. In addition, the related art counter is not capable of determining whether to continue counting from a suspended point or to restart counting.
The above references are incorporated by reference herein where appropriate for appropriate teachings of additional or alternative details, features and/or technical background.